Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process

Abstract:

This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, the proposed full adder is evaluated along with four existing full adders via extensive BSIM4 simulation. The simulation results, 180nm process models, indicate that the proposed design has lowest energy consumption per addition along with the performance edge in both speed and energy consumption makes it suitable for low power and high speed embedded processor applications.

• Periodical: Applied Mechanics and Materials (Volumes 284-287)
• Pages: 2580-2589
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.284-287.2580
• Online since: January 2013
• Authors: G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, T.S. Lim
• Keywords: Full-Adder, High-Speed, Low-Power, Monte-Carlo Analysis, Multiplexing, Pass Transistor Logic (PTL)

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