Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process

Abstract:

This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, the proposed full adder is evaluated along with four existing full adders via extensive BSIM4 simulation. The simulation results, 180nm process models, indicate that the proposed design has lowest energy consumption per addition along with the performance edge in both speed and energy consumption makes it suitable for low power and high speed embedded processor applications.

References

[1] V. G. Oklobdzija, B.R. Zeydal, H. Q. Dao, S. Mathew and R. Krishnamurthy: IEEE Trans. Very Large Scale Integration (VLSI) systems Vol. 13 (2005), p.754.

DOI: 10.1109/tvlsi.2005.848819

[2] K. Navi, O. Kavehei, M. Ruholamini, A. Sahafi, S. Mehrabi and N. Dadkhahi: J. Computers Vol. 3 (2008), p.48.

[3] T. Kuroda and M. Hamada: IEEE J. Solid-State Circuits Vol. 35 (2000), p.652.

[4] K. Usami and M. Horowitz: Proceedings of International Symposium on Low Power Electronics Design (California, USA, 1995), p.3.

[5] D. Marković, B. Nikolić and V.G. Oklobdžija: Microelectronics J Vol. 31 (2000), p.991.

[6] C. Senthilpari, K. Diwakar and A.K. Singh: J. Recent Patents on Nanotechnology Vol. 3 (2009), p.61.

[7] C. Senthilpari, S. Kavitha and J. Joseph: IEEE Proceedings of International Conference on Semiconductor Electronics (Melaka, Malaysia, 2010), p.140.

[8] C. Senthilpari, Z. M Irina and S. Kavitha: Microelectronics. J Vol. 42, (2011), p.445.

[9] G. Ramana Murthy, C. Senthilpari, P. Velrajkumar and T.S. Lim: IEEE Region 10 TENCON Conference (Bali, Indonesia, 2011), p.734.

[10] K. Navi, V. Foroutan, M. RahimiAzghadi, M. Maeen, M. Ebrahimpour, M. Kaveh and O. Kavehei: Microelectronics J Vol. 40 (2009), p.1441.

DOI: 10.1016/j.mejo.2009.06.005

[11] M. Alioto, G. Di Cataldob and G. Palumbo: Microelectronics J Vol. 38 (2007), p.130.

[12] Y. Wei and J. Shen: J. Zhejiang University Science C Vol. 12 (2011), p.604.

[13] F. Vasefi and Z. Abid: Proceedings of the International IEEE Conference on Electrical and Computer Engineering (Saskatoon, Sask, 2005), p.1731.

[14] M. N. Mahshid and K. Navi: J. Communication and Computer Vol. 7 (2010), p.1.

[15] V. Foroutan, K. Navi and M. Haghparast: World Applied Sciences J Vol. 4 (2008), p.133.

[16] M.H. Ghadiry, M. Nadisenejani and M. Miryahyaei: World Applied Sciences J Vol. 11 (2010), p.808.

[17] I. Hassoune, D. Flandre, I. O'Connor and J. D. Legat: IEEE Trans. Circuits and Systems-I: Regular Papers Vol. 57 (2010), p. (2066).

DOI: 10.1109/tcsi.2008.2001367

[18] W. Zhang, L. Li and J. Hu: International IEEE mid-west Symposium on Circuits and Systems (Cancun, Mexico, 2009), p.551.

[19] N.H.E. Weste and D. Harris: CMOS VLSI Design A Circuits and Systems Perspective (Addison Wesley, USA, 2005).