Development of an Economical Lapping Process

Mohamed Konneh; Afzeri Tamsir; Erry Yulian Triblas Adesta

doi:10.4028/www.scientific.net/AMR.472-475.2348

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 472-475Development of an Economical Lapping Process

Development of an Economical Lapping Process

Abstract:

The manufacturing of silicon wafers in particular involves numerous processes such as grinding, lapping, and polishing of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and/polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. This paper presents the development of a low cost lapping process, the process tried out on thin silicon chips that generated fracture-free with mirror-like surfaces of low roughness values and reasonably high degree of flatness.

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Advanced Manufacturing Technology, ICMSE 2012

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Periodical:

Advanced Materials Research (Volumes 472-475)

Pages:

2348-2353

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.472-475.2348

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Online since:

February 2012

Authors:

Mohamed Konneh, Afzeri Tamsir, Erry Yulian Triblas Adesta

Keywords:

Flatness, Lapping, Lapping Pressure, RSM, Silicon, Surface Roughness and Integrity

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References

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